1. Field of the Invention
Example embodiments of the present invention relate to an integrated circuit (IC) package, and more particularly, to a ball grid array type board on chip package and a method of manufacturing the same.
2. Description of the Related Art
A ball grid array type board on chip package may include an integrated circuit (IC) chip, which may be wire-bonded to a board through an opening formed through a center of the board. This board on chip package may be structurally vulnerable to a variety of forces, thereby providing a variety of reliability issues. The reliability issues may become more severe as processes of manufacturing the IC chip become more divided and involved.
FIG. 1 is a sectional view of a conventional ball grid array type board on chip package. Referring to FIG. 1, the board on chip package 101 may include an IC chip 111, a board 121 may be mounted on the IC chip 111 and a molding resin layer 131 may cover the IC chip 111.
A plurality of contact pads 113 (only one is shown) and a plurality of metal lines 115 may be formed on the IC chip 111. The contact pad 113 may be formed on a center of the IC chip 111. The metal lines 115 may be covered by an insulation layer 117.
The board 121 may support a plurality of solder balls 125 and a plurality of electrode pads 123. The electrode pads 123 may be electrically connected to the solder balls 125.
The board and the IC chip 111 may be adhered to each other by an adhesive material 141.
The contact pads 113 and the electrode pads 123 may be electrically interconnected by boding wires 151. The IC chip 111 may electrically interface an external device (not shown) through the bonding wires 151 and the solder balls 125.
The IC chip 111 and the bonding wires 151 may be molded by molding resin 131 and 133 to be protected from external environment.
According to the conventional board on chip package 101, the contact pad 113 may be disposed between the IC chip 111 and the board 121. The IC chip 111 may support the contact pad 113, which may be fabricated metal, and the insulation layer 117, which may fabricated from an insulating material. The IC chip 111 may be molded by the molding resin 131. Due to the mismatch between the different materials and stresses between the IC chip 111 and the board 121, stresses may be concentrated around the contact pad 113. As a result, delamination may be generated between the contact pad 113 and the insulation layer 117. Because the plurality of the contact pads 113 may be concentrated on the center of the IC chip 111, a metal region may occupy more than 60%. As a result, the delamination may be generated between the contact pads 113 and the insulation layer 117 even by a relatively small amount of the stress. Due to the delamination, the reliability of the board on chip package may be deteriorated. Delamination may cause the board on chip package 101 to be defective. In an attempt to reduce the delamination phenomenon, numerous and alternative metal line designs and/or metal line processes may have been implemented and various improvements may have been made to the metal line material, the molding resin and the adhesive materials. However, these propositions and improvement may not have sufficiently addressed the delamination problem.